Chips, Memory, and Power | Pat Gelsinger

AI chip design speed is outpacing fabrication, memory, power, and networking capacity, creating bottlenecks that will force industry consolidation and data-center project defaults.

• Nine-month bottleneck: Pat Gelsinger says AI can compress chip design to three months, but fabrication, advanced packaging, and rack-scale integration still take nine months, so designs risk obsolescence before deployment.
• HBM called 'hideous': He calls HBM memory the best available option despite shoreline bandwidth limits, power/thermal issues, and says there's been zero major new memory architecture in 30 years—until now.

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